Georgi Gaydadjiev: Multicores, Mayicores, KiloCore? What about no cores at all...

We leave in the era of core segregation on silicon. More and more cores doing simpler and simpler tasks co-exist on the surface of a given single chip. Architects' hope is that all these cores will not talk to each other or require a lot of synchronization. Experience tells that the number of real life applications with such properties is virtually non-existing. This situation is mainly due to the inertia of thinking,keep doing business as usual is very convenient. What about radically changing the game by placing the problem and more importantly the data to be processed in the middle and build the required solution around this with little or no restrictions imposed by various architectural and micro-architectural decisions done by someone else.

The streaming dataflow paradigm forms a promising solution for the data intensive parts of any application that is able to exploit all those great advantages offered by the steadily growing number of transistors per silicon unit area that manufacturing technologies are expected to deliver for at least few more generations. The dataflow approach brings its significant advantages by implicitly “hardening” all basic operations in its computational structure, tightly controlling and minimizing data movements at all levels, and by allowing highest degree of customization at very fine levels of granularity. Massive, deeply pipelined dataflow structures with at least thousands of pipeline stages can deliver unprecedented throughput advantages even running at an order of magnitude lower frequencies as compared to traditional systems. The programmability of such structures has been always challenging, however, Maxeler developed a working solution that resulted in successful acceleration of various problems in, among others, Geoscience, Financial Analytics, Cyber Security, Climate, Bioinformatics and High-Energy Physics. Our solution is built around a programming language called MaxJ and our fully programmable DataFlow Engines (DFEs) designed for streaming dataflow execution. MaxJ assumes all operations happen in space and by default are performed in parallel. It allows designers to partition, lay out and optimize their programs at all levels starting from the highest level of algorithmic transformations all the way down to individual custom bit manipulations. In addition, the execution model enforces highly efficient scheduling (or better called choreography) of all basic computational and data movement actions with the guarantee of no side effects. This approach is facilitated by a set of dedicated design tools and novel design methods along with a non-traditional way to measure (or rate) performance as compared to traditional approaches.

Our recent partnership with Amazon Web Services allowed us to extend the reach of our DFE technology to the public Cloud. In this talk we will address most of the topics relevant to spatial programming with MaxJ and its enormous capabilities to easily design power efficient, highly capable custom computing systems. We will show some examples and results gathered from real systems in use by Maxeler customers.

Georgi GaydadjievGeorgi Gaydadjiev is the Director of Maxeler IoT-Labs BV in the Netherlands and Honorary Visiting Professor in Computer Engineering at Imperial College in London. His research and development experience includes close to 30 years in hardware and software design at System Engineering Ltd. in Pravetz, Bulgaria, Pijnenburg Microelectronics and Software B.V. (later CPS BV) in Vught, TU Delft in the Netherlands and Chalmers University of Technology in Sweden. His research interests include reconfigurable computing systems, computer architecture and micro-architecture, embedded systems design, hardware/software co-design, and computer systems testing. Georgi served as a program chair of SAMOS 2006, the IEEE International Conference on Computer Design (ICCD) 2008 and 2009, Computing Frontiers 2009 and the IEEE Symposium on Application Specific Processors (SASP 2010). He was a general chair of SAMOS 2007, ICCD 2010 and 2011, and SASP 2011. In addition, he coordinated an 8.5 Million Euro European Commission funded research project on scalable computer architecture (SARC) successfully completed in March 2010. He received best paper awards from the International Conference on Supercomputing in 2010 and USENIX in 2006. Furthermore, he was a member of the HiPEAC Steering Committee